Architecture of High Performance Computers

Course: COL718
Semester II, 2016-17
Credits: 4 (3-0-2)



Instructor: Dr. Smruti R. Sarangi

Lectures
: Mon, Thu 9:30-10:50. 305 Bharti Building
Course Description: This course will give an introduction to designing and programming high performance processors.

Course Load: 1 Mid-term, 1 End-term, Minor 1(Assignment 1), Minor 2(Assignment 2),
                         and Assignment 3

Evaluation Midterm (20%), End term (25%), 3 Assignments (15% each), Attendance (10%)

Teaching Assistants Hameedah Sultan

Piazza discussion forum link  (access code: col718)

Textbook:
Background on processors and caches: Computer Organisation and Architecture, Smruti R. Sarangi, McGrawHill India. Link to buy. Slides, and videos (link)


S. No.
Date
Lecture
Slides
References
1
5th Jan
Course policies, Inorder pipelines, Performance Equation
OOO Execution - I Computer Organisation and Architecture
Chapter 9
2
9th Jan
Overview of branch prediction, renaming, precise interrupts


3
12th Jan
Branch Prediction

Two level prediction, Two level prediction-IIAgree predictor, General techniques, Three level adaptive
4
16th Jan
Register Renaming
OOO - II Processor microarchitecture book
Quantifying the complexity of superscalar processors
Design space of renaming techniques
5
Jan 19th
Wakeup, Bypass, Broadcast, Select


6
Jan 23rd
Load-Store Queue, Commit

Optimized Load Store Queue
7
Jan 28th
Recovery from speculation: RRF and RRAT, SRAM vs CAM based checkpoints


8
Jan 30th
ROB based OOO processor design
Little's Law
Intro. to scheduling and replay
OOO-III
Little's Law
9
Feb 6th
Non-Selective and Deferred Selective Replay

Scheduling and Replay
10
Feb 9th
Token based replay. Value prediction and instruction re-use mechanisms.

Load store speculation, store sets, dynamic dependence tracking, memory cloaking and bypassing
11
Feb 13th
SRAM and DRAM Cells
Chapter 6
(link)

12
Feb 16th
CAM Cells
Chapter 6

13
Feb 23rd
Instruction prefetching
Inst. Prefetching CGP, Markov, PIF, RDIP
14
6th Mar
Pentium Trace Cache

Trace cache patent
15
9th Mar
Date Prefetching
Data Prefetching Survey
16
13th Mar
Runahead Execution, Caches

Runahead Execution
17
16th Mar
Cache Design with Cacti
Caches Cacti Report, Multi core memory systems (book)
18
20th Mar
NUCA Caches

S-NUCA, R-NUCA
19
26th
Mar
Basics of On Chip Networks
Routing On chip networks (book)
20
27th Mar
Basics of Hardware Security (Prof. Kolin Paul)

Hardware Involved Software Attacks
21
3rd Apr
Routing and Flow Control
Flow Control
22
6th Apr
Flow Control


23
10th Apr
Design of Routers
Router Micro-arch Allocator Implementations
24
13th Apr
Coherence and Consistency
link to slides (Chapter 11) Primer on Cache Coherence and Memory Consistency(book)
25
17th Apr
Coherence Protocols: Write-update and Write-invalidate


26
24th Apr
Directory Coherence and Atomic Primitives
Directory Coherence
27
27th Apr
Memory Consistency Models
Memory Consistency
A Formal Hierarchy of Weak Memory Models (link)
Tutorial on Shared Memory Models (link)
28
29th Apr
Memory Consistency Models - II