Architecture of High Performance Computers

Course: COL718
Semester II, 2015-16
Credits: 4 (3-0-2)



Instructor: Dr. Smruti R. Sarangi

Lectures
: Mon, Thu 9:30-10:50. Seminar Room SIT Building

Course Description: This course will give an introduction to designing and programming high performance processors.

Course Load: 1 Mid-term, 1 End-term, Minor 1(Assignment 1), Minor 2(Assignment 2),
                         and Assignment 3

Teaching Assistants Pallavi Sethi, Hameedah Sultan, Rajshekar K.

Textbook:
Background on processors and caches: Computer Organisation and Architecture, Smruti R. Sarangi, McGrawHill India. Link to buy. Slides, and supplementary material (link)


S. No.
Date
Lecture
Slides
References
1
4th January
Course policies, Overview of the course

2
7th January
Basics of OOO execution. Idea of branch prediction.

Processor microarchitecture book
Quantifying the complexity of superscalar processors
3
11th January
Idea of renaming. Started branch prediction.
OOO Execution - I
Just the slides and relevant background
till this point
4
18th January
Branch Prediction

Two level prediction, Two level prediction-IIAgree predictor, General techniques, Three level adaptive
5
21st January
BTBs and Renaming
OOO - II

6
25th January
Renaming and Select

Design space of renaming techniques
7
28th January
Broadcast, Wakeup, and Bypass


8
1st Feb
Load-Store Queue and Commit

Optimized Load Store Queue
9
4th Feb
Commit and Recovery


10
8th Feb
Pipelines with rename buffers


11
15th Feb
Replay
OOO-III Scheduling and Replay
12
18th Feb
Selective Replay and Aggressive Speculation

Load store speculation, store sets, dynamic dependence tracking, memory cloaking and bypassing
13
22nd Feb
Background: SRAMs, DRAMs, caches

link to slides (Chapter 6)
14
25th Feb
Types of misses, victim cache, critical word first and early restart

Predecoding
15
7th Mar
Prefetching: Next line, Markov, CGP
Inst. Prefetching
CGP, Markov
16
14th Mar
Inst. Prefetching: PIF, RDIP, Trace Caches (P4)

PIF, RDIP, Trace cache patent
17
17th Mar
Data Prefetching
Data Prefetching
Survey, Runahead Execution
18
31st Mar
Cache Design
Caches
Cacti Report, Multi core memory systems (book)
19
2nd Apr
NUCA Schemes

S-NUCA, R-NUCA
20
4th Apr
Routing in NoCs
Routing
On chip networks (book)
21
7th Apr
Flow Control and Router Micro-architecture
Flow Control
Router Micro-arch

22
11th Apr
Router Micro-Architecture

Allocator Implementations
23
18th Apr
Multiprocessor Systems

link to slides (Chapter 11)
24
21 Apr
Coherence and Consistency (basics)

Primer on Cache Coherence and Memory Consistency(book)
25
25 Apr
Vector Processors and Directory Coherence
Directory Coherence
26
28 Apr
Memory Consistency
Memory Consistency Models
A Formal Hierarchy of Weak Memory Models (link)
Tutorial on Shared Memory Models (link)
27
30 Apr
Transactional Memory
Transactional Memory Transactional Memory (book)
28
2nd May
Final Wrap Up