Computer Architecture

Course: ELL 305
Semester I, 2019-20
Credits: 4 (3-0-2)



Instructor: Prof. Smruti R. Sarangi

Lectures: Tuesday, Wednesday and Friday: 10 AM to 11 AM, LHC 114
Piazza: http://piazza.com/iit_delhi/summer2019/ell305 (Access code is ell305)

Course Load: Minor 1, Minor 2, End term, 3 programming assignments
Office Hours: Friday 3 to 5 PM, (SIT 215)

Evaluation: 17.5% (Minor 1), 17.5% (Minor 2), 25% (Major), Assignments (12.5% + 12.5% + 15%)
Passing Criteria: At least 30% overall

Policy for late assignments and re-minor:
1. We will hold one re-minor for people who have missed one minor at the end of the major exam. Note that
to ensure a level playing field, it will be significantly harder than the original minor exams. The student needs
to show documentary evidence such as a medical certificate to the TA on the day of the reminor. Please don't
send any mails to the instructor or the TAs regarding this.

2. Every homework will have a deadline. Students can submit after the deadline: 20% penalty per day (rounded to
the next day --> 3 hours late implies 1 day late).


Teaching Assistants:

1. Hameedah Sultan (Head TA)
2. Priyanka Singla
3. Nivedita Shrivastava
4. Churchill Hemraj Khangar
5. Adeeb N. A.
6. Padala Suneel
7. Amit Kumar
8. Vaibhav Singh Khokhar
9. Saurabh Gupta
10. Shubham Sharma
11. Nirmal Sharma
Reference Books
[Textbook]  Computer Organisation and Architecture, Smruti R. Sarangi, McGrawHill 2015
                   Link to the homepage of the book [contains all the slides, and video lectures].


Lectures and Slides:

Date
 Lecture
 References/Remarks
23rd July
Course Policies
24th July
 Introduction: Design of a CPU (from a Turing machine)
 Chapter 1
26th July
 Number systems: sign-magnitude, 1's complement, bias (pros and cons)
 Chapter 2
30th July
 2's complement number system
31st July
 Representation of floating-point numbers
2nd Aug
 Denormal, double precision, and representation of strings
6th Aug
 Assembly language: format, register transfer notation, basic instructions, load and store
 Chapter 3
7th Aug
 Branch instructions. SimpleRisc code for a factorial function.
9th Aug
 Call and return instructions, recursive code for the factorial function
13th Aug
 Encoding instructions
16th Aug
 SRAM, DRAM, and CAM Cells
 Chapter 6
20th Aug
 Adders: carry select and carry lookahead
 Chapter 7
21st Aug
 Iterative and Booth Multipliers
Minor 1
30 Aug
 Minor 1 solutions, Wallace tree multiplier, Restoring division algorithm
31 Aug
 Non-restoring division [with the proof], and floating-point addition
3 Sept
 Floating-point addition/subtraction, and rounding
4 Sept
 Floating-point multiplication and division
6 Sept
 SimpleRisc Processor: IF to MA stages
 Chapter 8
7 Sept
 RW stage, control unit, data path, control path, introduction to pipelining
 Chapter 9
11 Sept
 Explanation of the 5 stages of the pipeline.
13 Sept
 Delayed branches, code reordering, and interlocks (branch and data)
17 Sept
 Forwarding
18 Sept
 Performance equations
20 Sept
 Performance equations - II
24 Sept
 Interrupt and exception handling

Minor 2
1 Oct
 Minor 2 solutions.Design of the memory system.
 Chapter 10
9th Oct
 Spatial locality, temporal locality, Fully associative caches
11th Oct
 Fully associative, set associative, and direct-mapped caches
15th Oct
 Performance model of memory systems
16th Oct
 Types of misses, memory system optimization techniques
18th Oct
 Virtual memory and paging
22 Oct
 TLB, swap space, shared memory, and protection
23rd Oct
[+extra classes]
 Parallel programming, Amdahl's law, Flynn's taxonomy, sequential consistency, coherence
weak consistency
 Chapter 11
25th Oct
 Snoopy coherence: Write-update and Write-invalidate protocols.
29th Oct
 Multithreading, Vector instructions
30th Oct
 GPUs
1st Nov
 Interconnects
13th Nov
 Course wrap-up, Chapter 12 [self-study component]